`timescale 1ns / 1ns
module tb_LC_3;
  reg CLK, RESET;
  LC_3 LC_3 (
      .RESET(RESET),
      .CLK  (CLK)
  );
  always #10 CLK = ~CLK;
  //assign RESET = 1;
  initial begin
    #0 RESET = 1;
    CLK = 1;
    #10 RESET = 0;
    //#2 RESET = 0;
    #1500 $finish;
  end
  initial begin
    $display("start a clock pulse");
    $dumpfile("tb_LC_3_5_16_new.vcd");
    $dumpvars(0, tb_LC_3);
  end
  //initial begin
  //  $fsdbDumpfile("tb_LC3.fsdb");
  //  $fsdbDumpvars;
  //end
endmodule
